this post was submitted on 11 Nov 2024
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Big brain tech dude got yet another clueless take over at HackerNews etc? Here's the place to vent. Orange site, VC foolishness, all welcome.

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[–] fasterandworse@awful.systems 7 points 1 week ago (10 children)

is this a possible thing: all the AI assistant stuff being forced onto us in the next gen hardware is gonna need significant computing power bumps to support it, is this creating a potential surplus of computing power in all devices that could time very well with an excessive skeuomorphic UI design response to the decade of bland flatness we've endured that's gonna cook the cpus on the devices of everyone else?

[–] froztbyte@awful.systems 6 points 1 week ago (3 children)

to the computing side, and with the proviso that in my own estimation of my skills I am at best slightly less than "dangerously clueless": unfortunately not as much as may be desired because the kind of chips being added are fairly specialised silicon

it's not impossible that people may find other uses for it over time but to the best of my knowledge as it stands right now much of this shit is dead weight the moment this bubble pops

(I don't think it will all go entirely away; there are some ML uses that are not complete trash. but that's a long different arc)

I'm not sure I follow the skeu side of your comment?

[–] istewart@awful.systems 6 points 1 week ago

My baseline understanding is that "NPUs," as such, are vector accelerators with perhaps lower precision and definitely lower peak TDP. I say this because much of the incremental ML research I've skimmed over seems to be around getting away with lower precision, dropping down to FP8 or even FP4 from FP16 when they can get away with it.

I'm still confused as to why and how this is an acceptable tradeoff to firing up an iGPU with precise power/TDP stepping. Perhaps one of those situations where the power budget and latency to fire up the whole GPU block or burst it to max power ends up costing as much as the actual calculation. I think for purposes of this discussion, we also need a source that sheds light on the architectural differences between NPUs and GPU shader/execution units.

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