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In what cases is a DRAM-less SSD good enough? (lemmy.ml)

submitted 8 months ago by geoma@lemmy.ml to c/hardware@lemmy.ml

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Where I live, DRAM-less SSDs are a lot cheaper (half the price). Most sources online say "go for an SSD with DRAM". But I wonder, are cases in which a DRAM-less SSD will do just fine?

My main focus is resurrecting old laptops (from 2006 to 2015), installing GNU/Linux and an sometimes investing in an SSD will give them a performance boost, but the budget is limited because I can't sella uch an old laptop at a non very budgety price.

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[–] ShortN0te@lemmy.ml 9 points 8 months ago (2 children)

As it was already commented Host Memory Buffer can to some degree replace the DRAM cache (if the SSD supports it and even then the implementation can be bad). But the specification is from 2014 so unlikely that Laptops from up to 2015 will support it.

When there is no DRAM cache on the SSD, the SSD will use the NAND flash cells as cache. This results in more wear and a shorter lifetime. Also, when the SSD gets filled up, the SSD gets significantly slower since there will be less free NAND cells to use as Cache.

[–] bazsy@lemmy.world 0 points 8 months ago (1 children)

I think calling it a "cache" is not precise. The primary function of the DRAM is to hold the dictionary for translating logical addresses (e.g. sectors) from the OS to the physical addresses (which NAND chip, which bank etc.). This indirection is needed for the controller to do wear leveling without corrupting the filesystem.

On a SATA SSD without DRAM each read IO could mean 2 actual reads: first the dictionary to find the data and than the actual data being read. As you said HBM helps by eliminating this extra read.

The read and write caching is just a use of the remaining DRAM capacity. Since modern Operating Systems use the general RAM for the same function it is usually just a small increase to the throughput.

[–] ShortN0te@lemmy.ml 2 points 8 months ago

The primary function of the DRAM is to hold the dictionary for translating logical addresses (e.g. sectors) from the OS to the physical addresses (which NAND chip, which bank etc.). This indirection is needed for the controller to do wear leveling without corrupting the filesystem.

That data is still only cached on the DRAM, since it is losing its data when it is no longer powered.